The present invention relates to an encoder and, more particularly, to an encoder which is suitable for use as the coding circuit of a parallel (flash) type high-speed AD converter (which will hereinafter be referred to as a "ADC").
Generally speaking, as shown in FIG. 9 parallel type ADCS are constructed, of a (2.sup.n -1) number of comparators 1 for comparing the reference voltages V.sub.j divided into (2.sup.n -1) levels with an analog input voltage V.sub.IN together with an encoder 2 for converting the output patterns of those comparators 1 into binary codes, where the letter n designates the number of output bits. Reference should be made to: (1) J. Peterson, "A monolithic Video A/D Converter", IEEE J. of Solid-Stage Circuit, vol. SC-14, No. 6, 1979; and (2) T. Takemoto et al., "A Fully Parallel 10 bit A/D converter with Video Speed", J. of Solid-State Circuit, Vol. SC-17. All the outputs of such, comparators take a high potential (which hereafter referred to as an "H"), in case the reference voltages V.sub.j are lower than the input voltage V.sub.IN, and a low potential (hereafter referred to as an "L") in the contrary case. The outputs of each pair of comparators made receptive of the reference voltages at the adjacent levels are examined by an exclusive OR circuit 2a in the encoder 2. As a result, only the exclusive OR circuit 2a corresponding to the position, in which the outputs of a series of comparators 1 change from the "L" to the "H", generates an "H" output, and all the others generate an "L" output. In other words, the exclusive OR circuit generating that "H" level corresponds to the level of the input voltage V.sub.IN. That "H" output is fed to an OR circuit 2b corresponding to each "1" bit position of the binary codes for expressing that level.
As the above-specified encoder constructed of the exclusive OR circuits 2a and the OR circuits 2b, there has been widely adopted, because of its remarkably simple circuit construction, a structure in which the outputs of the exclusive OR circuits are generated from the collectors of differential switching circuits and are fed to emitter-followers. The emitter-followers have emitters made receptive to the respective outputs of the exclusive OR circuits, and have their emitters connected mutually into a wired OR structure, as shown in FIG. 5. In this structure, the parasitic capacitance at the final stage creates a problem. If the output has 8 bits, for example, the number of transistors Q.sub.3 to be connected in parallel with one output bit line 21 may be as many as 2.sup.7 =128. The combined parasitic capacitances for the 128 circuits such as the emitter-base and base-collector capacitances of the transistors Q.sub.3 composing the emitter-follower or the collector-substrate capacitances of transistors Q.sub.2 relate to the output bit line 21. If the composed parasitic capacitance of one circuit is 0.1 to 0.2 pF. the total parasitic capacitance C.sub.eq related to the output bit line 21 may be as high as 10 to 20 pF. The load resistance RE of the emitter-follower cannot be made so low in relation to the power to be consumed or in relation to the driving ability of the previous stage circuit, and it may reache several K.OMEGA., if the current to be fed to the transistors Q.sub.3 is 1 mA and if the voltage of (V.sub.CC -V.sub.EE) is 5 V. If the load resistance is assumed to be 5 .OMEGA., its time constant .tau. with the total parasitic capacitance C.sub.eq reaches a value of 50 to 100 ns, which greatly restricts the speed of the whole ADC so that this speed is limited to several tens of MHz no matter how fast the comparators 1, the exclusive OR circuits and other circuits might be speeded up.